1 features applications description/ordering information SN74SSQE32882 www.ti.com ................................................................................................................................................. scas857a ? march 2008 ? revised october 2008 28-bit to 56-bit registered buffer with address parity test one pair to four pair differential clock pll driver the SN74SSQE32882 has two basic modes of operation associated with the quad chip select 2 jedec sste32882 compliant enable ( qcsen) input. 1-to-2 register outputs and 1-to-4 clock pair first, when the qcsen input pin is open or pulled outputs support stacked ddr3 dimms high, the component has two chip select inputs, chip select inputs prevent data outputs from dcs0 and dcs1, and two copies of each chip select changing state and minimize system power output, qacs0, qacs1, qbcs0 and qbcs1. this consumption mode is the quadcs disabled mode. alternatively, when the qcsen input pin is pulled low, the 1.5-v phase lock loop clock driver buffers component has four chip select inputs dcs[3:0], and one differential clock pair (ck and ck) and four chip select outputs, qcs[3:0]. this mode is the distributes to four differential outputs quadcs enabled mode. 1.5-v cmos inputs when qcsen is high or floating, the device also checks parity on command and address supports an operating mode that allows a single (cs-gated) data inputs device to be mounted on the back side of a dimm supports lvcmos switching levels on array. this device can then be configured to keep the reset input input bus termination (ibt) feature enabled for all input signals independent of mirror. the reset input: SN74SSQE32882. operates from a differential clock ? disables differential input receivers (ck and ck). data are registered at the crossing of ? resets all registers ck going high and ck going low. this data can either be re-driven to the outputs or used to access internal ? forces all outputs into pre-defined states control registers. details are covered in the function optimal pinout for ddr3 dimm pcb layout tables (each flip-flop) with qcsen = low. supports four chip selects input bus data integrity is protected by a parity single register backside mount support function. all address and command input signals are summed; the last bit of the sum is then compared to the parity signal delivered by the system at the ddr3 registered dimms up to ddr3-1333 par_in input one clock cycle later. if these two values do not match, the device pulls the open drain single-, dual- and quad-rank rdimm output errout low. the control signals (dcke0, dcke1, dodt0, dodt1, and dcs[n:0]) are not part of this computation. this jedec sste32882-compliant, 28-bit 1:2 or the SN74SSQE32882 implements different 26-bit 1:2 and 4-bit 1:1 registering clock driver with power-saving mechanisms to reduce thermal power parity is designed for operation on ddr3 registered dissipation and to support system power-down states. dimms up to ddr3-1333 with v dd of 1.5 v. power consumption is further reduced by disabling all inputs are 1.5-v, cmos-compatible. all outputs unused outputs. are 1.5-v cmos drivers optimized to drive dram the package design is optimal for high-density signals on terminated traces in ddr3 rdimm dimms. by aligning input and output positions applications. clock outputs yn and yn and control net towards dimm finger-signal ordering and sdram outputs dxcken, dxcsn, and dxodtn can each be ballout, the device de-scrambles the dimm traces driven with a different strength and skew to optimize and allows low crosstalk designs with low signal integrity, compensate for different loading, and interconnect latency. edge-controlled outputs reduce balance signal travel speed. ringing and improve signal eye opening at the sdram inputs. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
electrical characteristics absolute maximum ratings SN74SSQE32882 scas857a ? march 2008 ? revised october 2008 ................................................................................................................................................. www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information (1) orderable top-side t case package (2) part number marking 0 c - t case 176zal tape and reel SN74SSQE32882zalr te32882e (see table 1 ) 176zcj tape and reel SN74SSQE32882zcjr te32882e (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. over operating free-air temperature range (unless otherwise noted). (1) parameter value unit v dd supply voltage ? 0.4 to +1.975 v v i receiver input voltage see (2) and (3) ? 0.4 to v dd + 0.5 v v ref reference voltage ? 0.4 to v dd + 0.5 v v o driver output voltage see (2) and (3) ? 0.4 to v dd + 0.5 v i ik input clamp current v i < 0 or v i > v dd ? 50 ma i ok output clamp current v o < 0 or v o > v dd 50 ma i o continuous output current 0 < v o < v dd 50 ma i ccc continuous current through each v dd or gnd pin 100 ma t stg storage temperature ? 65 to +150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) this value is limited to 2.2 v maximum. table 1. case temperature vs speed node parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit t case maximum case temperature (1) +109 +108 +106 +103 c (1) the temperature values fit to jedec raw cards a, b, and c. the user must keep t case below the specified values in order to keep the junction temperature below +125 c. other combinations of features and termination resistors can require lower case temperature and extra cooling. these combinations depend on the specific application. 2 submit documentation feedback copyright ? 2008, texas instruments incorporated
package information zal package SN74SSQE32882 www.ti.com ................................................................................................................................................. scas857a ? march 2008 ? revised october 2008 the package is an 8-mm 13.5-mm, 176-pin ball grid array (bga) with 0.65-mm ball pitch in an 11 20 grid. the device pinout supports outputs on the outer two left and right columns to support easy dimm signal routing. corresponding inputs are placed in such a way that two devices can be placed back-to-back for four rank modules while the data inputs share the same vias. each input and output is located close to an associated no-ball position or on the outer two rows to allow for low-cost via technology combined with the small, 0.65-mm ball pitch. copyright ? 2008, texas instruments incorporated submit documentation feedback 3 1 2 3 4 5 6 7 8 9 10 11 ab c d e f g h j k l m n p r t u v w y
zcj package SN74SSQE32882 scas857a ? march 2008 ? revised october 2008 ................................................................................................................................................. www.ti.com the package is an 6-mm 15-mm, 176-pin ball grid array (bga) with 0.65-mm ball pitch in an 8 22 grid. the device pinout supports outputs on the outer two left and right columns to support easy dimm signal routing. corresponding inputs are placed in such a way that two devices can be placed back-to-back for four rank modules while the data inputs share the same vias. note: to request more information on SN74SSQE32882 ddr3 register/pll please contact support@ti.com . 4 submit documentation feedback copyright ? 2008, texas instruments incorporated 1 2 3 4 5 6 7 8 a b c d e f g h j k l m n p r t u v w y aa ab
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa00441zalr nrnd nfbga zal 176 2000 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 85 te32882e SN74SSQE32882zalr nrnd nfbga zal 176 2000 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 85 te32882e (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74SSQE32882zalr nfbga zal 176 2000 330.0 24.4 8.3 13.8 1.8 12.0 24.0 q1 package materials information www.ti.com 12-may-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74SSQE32882zalr nfbga zal 176 2000 336.6 336.6 31.8 package materials information www.ti.com 12-may-2017 pack materials-page 2
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